Is there any way to know the size of L1, L2, L3 cache and RAM in ubuntu?

Any terminal command or files I could look into?

CPU information

Use the lscpu command:

$ lscpu

Architecture:          x86_64

CPU op-mode(s):        32-bit, 64-bit

Byte Order:            Little Endian

CPU(s):                2

On-line CPU(s) list:   0,1

Thread(s) per core:    1

Core(s) per socket:    2

Socket(s):             1

NUMA node(s):          1

Vendor ID:             GenuineIntel

CPU family:            15

Model:                 6

Stepping:              5

CPU MHz:               2400.000

BogoMIPS:              6000.33

L1d cache:             16K

L2 cache:              2048K

NUMA node0 CPU(s):     0,1

Listed information is per CPU-core.

Memory information

There is the free command (-h gives results in human readable form, i.e. GiB rather then bytes):

$ free -h

             total       used       free     shared    buffers     cached

Mem:          2.0G       390M       1.6G        10M        15M       160M

-/+ buffers/cache:       215M       1.7G

Swap:         2.0G         0B       2.0G

This will give you your cache information. Socket Designation will tell you which cache is being referred to in the section.

sudo dmidecode -t cache

For RAM there are a couple things to look at but meminfo should do it. I used grep here to only show total/free but you could use less or cat to see the whole thing. It shows a lot more information on memory size and usage than just size.

grep Mem /proc/meminfo

Based on jkabrams answer with following command and filtering "cache" from it, each cache item you have be shown.

lscpu | grep cache

and RAM:

free -h

For more information about RAM, processes and so on you can use htop on your distro. Install it like this on ubuntu.

sudo apt-get install htop

sysfs

for d in /sys/devices/system/cpu/cpu0/cache/index*;

  do tail -c+1 $d/{level,type,size}

  echo

done

Gives:

==> /sys/devices/system/cpu/cpu0/cache/index0/level <==

1



==> /sys/devices/system/cpu/cpu0/cache/index0/type <==

Data



==> /sys/devices/system/cpu/cpu0/cache/index0/size <==

32K



==> /sys/devices/system/cpu/cpu0/cache/index1/level <==

1



==> /sys/devices/system/cpu/cpu0/cache/index1/type <==

Instruction



==> /sys/devices/system/cpu/cpu0/cache/index1/size <==

32K



==> /sys/devices/system/cpu/cpu0/cache/index2/level <==

2



==> /sys/devices/system/cpu/cpu0/cache/index2/type <==

Unified



==> /sys/devices/system/cpu/cpu0/cache/index2/size <==

256K



==> /sys/devices/system/cpu/cpu0/cache/index3/level <==

3



==> /sys/devices/system/cpu/cpu0/cache/index3/type <==

Unified



==> /sys/devices/system/cpu/cpu0/cache/index3/size <==

8192K

getconf

getconf -a | grep CACHE

gives:

LEVEL1_ICACHE_SIZE                 32768

LEVEL1_ICACHE_ASSOC                8

LEVEL1_ICACHE_LINESIZE             64

LEVEL1_DCACHE_SIZE                 32768

LEVEL1_DCACHE_ASSOC                8

LEVEL1_DCACHE_LINESIZE             64

LEVEL2_CACHE_SIZE                  262144

LEVEL2_CACHE_ASSOC                 8

LEVEL2_CACHE_LINESIZE              64

LEVEL3_CACHE_SIZE                  20971520

LEVEL3_CACHE_ASSOC                 20

LEVEL3_CACHE_LINESIZE              64

LEVEL4_CACHE_SIZE                  0

LEVEL4_CACHE_ASSOC                 0

LEVEL4_CACHE_LINESIZE              0

Or for a single level:

getconf LEVEL2_CACHE_SIZE

The cool thing about this interface is that it is just a wrapper around the POSIX sysconf C function (cache arguments are non-POSIX extensions), and so it can be used from C code as well.

Tested in Ubuntu 16.04.

x86 CPUID instruction

The CPUID x86 instruction also offers cache information, and can be directly accessed by userland: https://en.wikipedia.org/wiki/CPUID

glibc seems to use that method for x86. I haven't confirmed by step debugging / instruction tracing, but the source for 2.28 sysdeps/x86/cacheinfo.c does that:

__cpuid (2, eax, ebx, ecx, edx);

TODO create a minimal C example, lazy now, asked at: https://stackoverflow.com/questions/14283171/how-to-receive-l1-l2-l3-cache-size-using-cpuid-instruction-in-x86

ARM also has an architecture-defined mechanism to find cache sizes through registers such as the Cache Size ID Register (CCSIDR), see the ARMv8 Programmers' Manual 11.6 "Cache discovery" for an overview.