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I'm currently trying to find out whether or not it would be a good idea to update my slightly dated notebook (Windows 7, 64-bit) to Windows 10. The problem is that Microsoft states in their Windows 10 specifications that to use the 64-bit version of Windows 10, a processor which supports CMPXCHG16b, PrefetchW and LAHF/SAHF is needed. I know that my processor is 64-bit (Intel Core i5-2430M @ 2.40 GHz) but I don't know how to find out whether it supports CMPXCHG16b, PrefetchW and LAHF/SAHF, and I have no idea what these mean.

I tried using Google and got no results that made sense to me, only some comparison of my i5 and a similar AMD processor. I also checked Intel's ARK website. If somebody could point me to where I can get more info I would be really grateful.

Your processor supports these features. In fact, the same features are required to run 64-bit Windows 8.1. This requirement is met by all modern processors and is generally only an issue with certain Core 2 and earlier processors.

What are these instructions?

• The CMPXCHG16B instruction performs an atomic compare-and-exchange on 16-byte values. It is supported on all modern x86-64 processors, although some early AMD64 CPUs did not support it. This instruction may also be referred to as CompareExchange128. See also: How prevalent are old x64 processors lacking the cmpxchg16b instruction?
  

• Early AMD64 processors lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post-80486 processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic operations on octal words. This is useful for parallel algorithms that use compare and swap on data larger than the size of a pointer, common in lock-free and wait-free algorithms. Without CMPXCHG16B one must use workarounds, such as a critical section or alternative lock-free approaches. Its absence also prevents 64-bit Windows prior to Windows 8.1 from having a user-mode address space larger than 8 terabytes. The 64-bit version of Windows 8.1 requires the instruction.

• The PREFETCHW instruction is a hint to the processor to prefetch data from memory into the cache in anticipation for writing (Intel Instruction Set Reference, PDF page 888). This instruction was introduced in AMD's 3DNow! instruction set, which is deprecated except for the PREFETCH and PREFETCHW instructions. All AMD processors since the Athlon 64 support this instruction. However, this instruction may not be supported in some older 64-bit Intel processors predating Nehalem.




• The LAHF and SAHF load and store the contents of the AH register into the flags register, respectively (Intel Instruction Set Reference, PDF pages 530 and 1025). Some older Intel processors without hardware virtualization (VT-x) functionality do not support this instruction when running in 64-bit long mode; these are mostly limited to certain low-end processors predating Nehalem. Some very old AMD64 processors also lack this feature.

• Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions in 64-bit mode. AMD introduced these instructions (also in 64-bit mode) with their Athlon 64, Opteron and Turion 64 revision D processors in March 2005 while Intel introduced the instructions with the Pentium 4 G1 stepping in December 2005. The 64-bit version of Windows 8.1 requires this feature.

What does this mean for me?

• All Intel Core i7, i5, or i3 processors, as well as all Pentium or Celeron processors based on the Clarkdale, Arrandale, Sandy Bridge, or newer microarchitectures, support these features, as well as Intel Atom and Celeron Silvermont processors. For AMD, all but the oldest 64-bit processors have these features.




• You generally only need to be concerned about these instructions if you have a processor that predates the above. The Get Windows 10 app will tell you if you can upgrade to Windows 10. If the processor doesn't meet requirements, you'll get "The CPU isn't supported."

If you can use the command line in Windows then:

• Get SysInternals coreinfo.exe from technet
  


• Run coreinfo > coreinfo.txt
  


• Open the file in a text editor, and do a find (case insensitive) for each of the instructions

PS: In Linux you would use grep flags /proc/cpuinfo | head -1

There is a utility called coreinfo, provided by Microsoft, that provides functionality like cat /proc/cpuinfo on Linux.

You have to search through this but you can find the information here,

LAHF-SAHF       -       Supports LAHF/SAHF instructions in 64-bit mode

NX              -       Supports no-execute page protection

CX16            *       Supports CMPXCHG16B instruction

X64             *       Supports 64-bit mode

PREFETCHW       -       Supports PREFETCHW instruction

The - mean that the CPU lacks that feature, the * mean it has that feature.

Now that I look, coreinfo is actually suggested by Microsoft to make the determination on that doc page,

Coreinfo is a tool you can use to confirm which of these capabilities your CPU has.+

Full result for my processor, a Intel E7525, looks like this,

Coreinfo v3.31 - Dump information on system CPU and memory topology

Copyright (C) 2008-2014 Mark Russinovich

Sysinternals - www.sysinternals.com



Intel(R) Xeon(TM) CPU 3.40GHz

x86 Family 15 Model 4 Stepping 3, GenuineIntel

Microcode signature: 00000005

HTT             *       Hyperthreading enabled

HYPERVISOR      -       Hypervisor is present

VMX             -       Supports Intel hardware-assisted virtualization

SVM             -       Supports AMD hardware-assisted virtualization

X64             *       Supports 64-bit mode



SMX             -       Supports Intel trusted execution

SKINIT          -       Supports AMD SKINIT



NX              -       Supports no-execute page protection

SMEP            -       Supports Supervisor Mode Execution Prevention

SMAP            -       Supports Supervisor Mode Access Prevention

PAGE1GB         -       Supports 1 GB large pages

PAE             *       Supports > 32-bit physical addresses

PAT             *       Supports Page Attribute Table

PSE             *       Supports 4 MB pages

PSE36           *       Supports > 32-bit address 4 MB pages

PGE             *       Supports global bit in page tables

SS              *       Supports bus snooping for cache operations

VME             *       Supports Virtual-8086 mode

RDWRFSGSBASE    -       Supports direct GS/FS base access



FPU             *       Implements i387 floating point instructions

MMX             *       Supports MMX instruction set

MMXEXT          -       Implements AMD MMX extensions

3DNOW           -       Supports 3DNow! instructions

3DNOWEXT        -       Supports 3DNow! extension instructions

SSE             *       Supports Streaming SIMD Extensions

SSE2            *       Supports Streaming SIMD Extensions 2

SSE3            *       Supports Streaming SIMD Extensions 3

SSSE3           -       Supports Supplemental SIMD Extensions 3

SSE4a           -       Supports Streaming SIMDR Extensions 4a

SSE4.1          -       Supports Streaming SIMD Extensions 4.1

SSE4.2          -       Supports Streaming SIMD Extensions 4.2



AES             -       Supports AES extensions

AVX             -       Supports AVX intruction extensions

FMA             -       Supports FMA extensions using YMM state

MSR             *       Implements RDMSR/WRMSR instructions

MTRR            *       Supports Memory Type Range Registers

XSAVE           -       Supports XSAVE/XRSTOR instructions

OSXSAVE         -       Supports XSETBV/XGETBV instructions

RDRAND          -       Supports RDRAND instruction

RDSEED          -       Supports RDSEED instruction



CMOV            *       Supports CMOVcc instruction

CLFSH           *       Supports CLFLUSH instruction

CX8             *       Supports compare and exchange 8-byte instructions

CX16            *       Supports CMPXCHG16B instruction

BMI1            -       Supports bit manipulation extensions 1

BMI2            -       Supports bit manipulation extensions 2

ADX             -       Supports ADCX/ADOX instructions

DCA             -       Supports prefetch from memory-mapped device

F16C            -       Supports half-precision instruction

FXSR            *       Supports FXSAVE/FXSTOR instructions

FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction

MONITOR         *       Supports MONITOR and MWAIT instructions

MOVBE           -       Supports MOVBE instruction

ERMSB           -       Supports Enhanced REP MOVSB/STOSB

PCLMULDQ        -       Supports PCLMULDQ instruction

POPCNT          -       Supports POPCNT instruction

LZCNT           -       Supports LZCNT instruction

SEP             *       Supports fast system call instructions

LAHF-SAHF       -       Supports LAHF/SAHF instructions in 64-bit mode

HLE             -       Supports Hardware Lock Elision instructions

RTM             -       Supports Restricted Transactional Memory instructions



DE              *       Supports I/O breakpoints including CR4.DE

DTES64          *       Can write history of 64-bit branch addresses

DS              *       Implements memory-resident debug buffer

DS-CPL          *       Supports Debug Store feature with CPL

PCID            -       Supports PCIDs and settable CR4.PCIDE

INVPCID         -       Supports INVPCID instruction

PDCM            -       Supports Performance Capabilities MSR

RDTSCP          -       Supports RDTSCP instruction

TSC             *       Supports RDTSC instruction

TSC-DEADLINE    -       Local APIC supports one-shot deadline timer

TSC-INVARIANT   -       TSC runs at constant rate

xTPR            *       Supports disabling task priority messages



EIST            *       Supports Enhanced Intel Speedstep

ACPI            *       Implements MSR for power management

TM              *       Implements thermal monitor circuitry

TM2             -       Implements Thermal Monitor 2 control

APIC            *       Implements software-accessible local APIC

x2APIC          -       Supports x2APIC



CNXT-ID         *       L1 data cache mode adaptive or BIOS



MCE             *       Supports Machine Check, INT18 and CR4.MCE

MCA             *       Implements Machine Check Architecture

PBE             *       Supports use of FERR#/PBE# pin



PSN             -       Implements 96-bit processor serial number



PREFETCHW       -       Supports PREFETCHW instruction



Maximum implemented CPUID leaves: 00000005 (Basic), 80000008 (Extended).



Logical to Physical Processor Map:

*-  Physical Processor 0

-*  Physical Processor 1



Logical Processor to Socket Map:



Logical Processor to NUMA Node Map:

**  NUMA Node 0



Logical Processor to Cache Map:

"Intel(R) Core(TM) i7-2600K CPU @ 3.40GHz"

"PREFETCHWT1 Instruction Not Supported"

From AIDA 64 Extreme. ^^

These three - CMPXCHG16b, PrefetchW and LAHF/SAHF are required for upgrade to a 64bit version of Windows 10 from a current 64bit installation of Windows 7.